The present invention relates to an improvement of techniques for constructing a receiver circuit for receiving a packet FSK (Frequency Shift Keying) signal by a receiver having frequency scanning faculty.
There are various kinds of FSK signals that include packets. One of them is a packet signal of such type that a center frequency is provided in a head or an overhead portion of the packet.
For a FSK signal of a packet type having frequency error, in general, first frequency scanning of a local oscillator is done and then, when the IF (Intermediate Frequency) frequency of a received signal obtained thereby comes within the pass band of an IF filter, a carrier detector detects this situation to stop the frequency scanning. However, at this time, ordinarily, the frequency of the IF signal does not coincide with that of an object signal, so frequency error remains. So, it is necessary to remove this frequency error by causing an AFC (Automatic Frequency Control) circuit to operate at the same time while stopping frequency scanning or to correct a DC offset component provided in a base band portion owing to remaining frequency error by a suitable correcting circuit.
Various correcting circuits for a signal having such packet construction that a bit synchronizing signal is provided in an overhead portion of the packet are proposed to attain the above mentioned object.
Following are known correcting methods employed in these correcting circuits.
As representatives thereof there are known 1) a method in which there are disposed a positive and a negative peak hold circuit and the center level is obtained, starting from an average of peak values held therein; 2) a method in which there are disposed a positive and a negative dead zone circuit having dead zone voltage widths, which are in accordance with a positive and a negative peak value width, respectively, of the base band signal, and the center error is obtained by taking out components output, exceeding these dead zone voltage widths, in the base band signal; 3) a method in which the center level is obtained by integrating a bit synchronizing signal, which is at a beginning of the packet signal, over a 2 bit length (a period of time of 2/baud sec (baud being transmission speed)); 4) a method in which the bit synchronizing signal is sampled twice with an interval of 1/baud sec and the center level is obtained, starting from an average of these sampled values; etc.
Since these methods are correcting methods suitable for a packet signal having only a true FSK signal without a center frequency signal in a head thereof, the frequency error of the FSK signal can not be corrected by method (1) or (2), but can be corrected roughly by method (3) or (4).
However, in a case that center frequency can be used, since center frequency error is obtained directly, it is apparent that a correcting circuit can be constructed more simply by other correcting methods than method (3) or (4).
As such method, we filed U.S. patent application Ser. No. 09/259,633 on Feb. 26, 1999, now U.S. Pat. No. 6,396,882, corresponding to Japanese Patent Application No. 10-150685 in which, when a center frequency signal in a head of a packet is demodulated by frequency scanning to provide a base band signal and this base band signal passes through a judgment threshold for a FSK signal, this passing moment is detected to render a scanning frequence of a scanning oscillator hold and at the same time, scanning stop.
However, according to this correct method, it is necessary to take response times of a threshold passing detection circuit, a hold control circuit and a hold circuit itself until the scanning oscillator is held after the base band signal passes through the threshold. Further, the scanning oscillator produces a scanning signal having a frequency which leads by a signal transmission delay time (a delay time from the scanning oscillator to a frequency discriminator) already when it is detected that the base band signal passes through the threshold. Accordingly, according to the above mentioned method, a frequency which overpasses by all response times of a system (a loop delay time) from a true central frequency is set and held. If this overpassing quantity of the set frequency is large, demodulation margin reduces, or if a scanning speed is slowed down to make it be small, it is necessary to set a long duration to issue the center frequency and as a result, through-put of transmission data reduces.
An object of the invention is to provide a frequency scanning FSK receiver capable of holding a correct scanning frequency which coincides with said center frequency irrespective of the loop delay time of a receiver system owing to response times of a threshold passing detection circuit (a converting point detector), a hold control circuit and a hold circuit, and transmission time of an IF amplifier in order to solve the above mentioned problem.
In order to attain the above object, the present invention is characterized by a frequency scanning receiver for a FSK signal of a packet type, the packet having a duration when center frequency is provided in a head portion thereof. A conversion point detecting means detects a time point when a demodulated base band signal obtained by demodulating the FSK signal passes through a conversion point at a time of the duration; holding means for holding a scanning voltage to scan the FSK signal at the time point; and correcting means for providing a correction signal having an overpassing quantity of scan corresponding to a loop delay time of a system of the receiver and a scanning speed.
In the above frequency scanning receiver of the invention said conversion point detecting means may comprise a comparator for comparing the demodulated base band signal with a reference voltage. A carrier detector for detecting existence of said demodulated base band signal or an IF signal, a conversion point detector for detecting inversion of an output of the comparator at the time point and a flip-flop circuit set by an output of the conversion point detector and reset by an output of the carrier detector provided when there is no demodulated base band signal or IF signal, and said holding means may include a hold circuit for holding sample value of the scanning voltage in response to a set output of said flip-flop circuit, and wherein said correcting means comprises a flip-flop circuit for latching the output of said comparator or a scanning direction-signal until end of a packet, a weighting circuit for weighting an output of said flip-flop circuit and a circuit for adding an output correcting-voltage of said weighting circuit to said scanning voltage.
Further in the above frequency scanning receiver may comprise a rectangular wave signal generator and an integrator for integrating the rectangular wave signal from said generator to provide the scanning voltage, the rectangular wave signal being used as said scanning direction signal.